In the clock signal synthesizer of a mainboard, a phase-locked loop is often utilized to correctly recover data. Moreover, a modification is often made to a phase-locked loop so that frequency expansion can be achieved for the purpose of reducing electromagnetic is interference (EMI) significantly. However, there is no simple solution in the prior art that provides a phase-locked loop with frequency expansion capability.
FIG. 1 illustrates a conventional phase-locked loop comprising a divided-by-N counter 11, a divided-by-M counter 12, a phase frequency detector 13, a charge pump 14, a loop filter 15, and a voltage controlled oscillator 16.
The divided-by-N counter 11 outputs a clock signal (it will be denoted by f.sub.xtal /N in the following) with frequency 1/N that of the input clock signal f.sub.xtal. FIG. 2 illustrates the situations that the frequency of an input clock signal is divided by 2 and 3 respectively. The divided-by-M counter 12 outputs a clock signal (it will be denoted by f.sub.vco /M in the following) with frequency 1/M that of the input clock signal f.sub.vco. The phase frequency detector 13 outputs voltage signals (up dn) which are determined by the frequency difference and phase difference of the two input signals f.sub.xtal /N and f.sub.vco /M. As shown in FIG. 3(a), when the phase of f.sub.vco /M lags behind that of f.sub.xtal /N (as denoted in the figure by dotted lines), the phase frequency detector 13 outputs an `up` signal. On the other hand, as shown in FIG. 3(b), when the phase of f.sub.vco /M leads that of f.sub.xtal /N (as denoted in the figure by dotted lines), the phase frequency detector 13 outputs a `dn` signal. Referring to FIG. 4, the charge pump 14 and the loop filter 15 cooperatively convert the `up` and `dn` signals outputted from the phase frequency detector 13 into a voltage signal Vc. When the phase frequency detector 13 outputs an `up` signal, the upper switch in the charge pump 14 is ON and current flows into the loop filter 15. The output voltage Vc of the loop filter 15 is raised. On the other hand, when the phase frequency detector 13 outputs an `dn` signal, the lower switch in the charge pump 14 is ON and current flows from the loop filter 15 to the lower current source. The output voltage Vc of the loop filter 15 is lowered. The voltage controlled oscillator 16 outputs a clock signal with frequency f.sub.vco determined by the output voltage V.sub.c from the loop filter 15. The frequency f.sub.vco increases as V.sub.c increases, and f.sub.vco decreases as V.sub.c decreases.
As described above, when the phase-locked loop 1 is in a phase-locked state, the phase of f.sub.xtal /N is in alignment with that of f.sub.vco /M and and the frequencies of these two clock signals are the same, as shown in FIG. 5. In other words, f.sub.vco =(M/N).times.f.sub.xtal. It can be seen from this relation that the f.sub.vco can be determined by M and N.
The concept of frequency expansion is described in the following. Assume that a clock signal with certain fixed frequency is desired, then clock signals with frequency varies in a predetermined frequency range centering at that frequency is generated. For example, frequency may vary linearly and periodically in a predetermined frequency range. Referring to FIG. 1, the frequency f.sub.vco can be made to vary linearly and periodically by making Vc vary linearly and periodically, which can be derived if the `up` and `dn` signals vary alternately and periodically. Moreover, the `up` and `dn` signals may be made to vary alternately and periodically by adjusting the values of M and/or N. As shown in FIG. 5, while the phase-locked loop 1 is in a phase-locked state, the phase of f.sub.xtal /N is in alignment with that of f.sub.vco /M and there is no `up` or `dn` signal generated. Referring to FIG. 6, when the value of M is suddenly changed to (M+.DELTA.M) or (M-.DELTA.M), the `up` and `dn` signals are alternately generated. Similarly, when the value of N is suddenly changed to (N+.DELTA.N) or (N-.DELTA.N), the `up` and `dn` signals are alternately generated as well.
As described above, changing the value of M (or N) results in the `up` and `dn` signals being generated alternately. This in turn makes Vc vary linearly and periodically. Consequently, the value of f.sub.vco varies linearly and periodically. FIG. 7 shows the variation of f.sub.vco when M varies through a series of increments (.DELTA.M) and then a series of decrements (-.DELTA.M). From the figure, it can be seen that f.sub.vco varies linearly and periodically in a predetermined frequency range centering at the frequency f.
From the above description, it can be seen that a phase-locked loop can achieve the effect of frequency expansion by changing the values of M and N. However, changing the values of M and N is not easy and may require a quite complicated circuit.